One of the more important applications for integrated circuit memory devices is in the field of image processing. In an image processing system, a video sensing device (e.g., an array of charge coupled devices or a video camera) typically produces image data as an analog signal that is digitized by an analog-to-digital (A-D) converter and stored in a memory circuit in a pixel representation, as a two-dimensional array of gray scale values. Efficient processing of the image data is often best implemented on bit-serial arithmetic units (processors), which offer the advantages of variable sized arguments and a small number of input/output pins. The bit-serial processors require the image data to be read one bit (bit plane) at a time so that their input is a serial data stream, starting with the least significant bit (LSB) and proceeding through the most significant bit (MSB) by taking successive bit slices of the pixels. By using one bit-serial processor for each column of the image, one row of a bit plane image can be read at a time, as each bit-serial processor simultaneously receives a bit of the same significance (e.g., the fifth bit of all of the pixels on a row). Unfortunately, use of bit-serial processors requires that information comprising the image data be converted from the pixel representation to the bit plane representation, and then back to pixel representation, for display on a monitor.
For example, the pixel representation of image data may comprises a 128.times.128 array of eight-bit pixels. In contrast, the corresponding bit plane representation of this image data would be eight bit planes, each including a 128.times.128 array of one-bit data.
Clearly, the pixel representation and the bit plane representation of image data are different formats that require accessing the bits of the image data differently. Thus, a typical image processing system uses a number of serial-to-parallel and parallel-to-serial converters to convert image data between the two representations. Provision of a memory circuit that eliminates the need for such conversions and allows both pixel and bit slice data to be stored and retrieved as parallel data would thus contribute a significant improvement to the current state of the art by enhancing the speed with which the image data are stored and accessed, particularly for the bit plane representation.
Presently, memory devices are not commercially available that can access data stored in memory selectively in either a pixel or a bit plane representation. In U.S. Pat. No. 4,641,282, a memory system is disclosed for use in a display or printing system for processing graphics data. The memory system has a plurality of memory planes, each provided with an operation circuit that performs logical operations on the picture data stored in each memory plane and simultaneously writes the results in the memory planes. However, there is no provision for reading the memory planes as gray scale data, i.e., there is no access to the data in a parallel format, in pixel representation.
In U.S. Pat. No. 4,623,990, a single-array memory includes a storage cell providing dual read/write access via either an "A" side or a "B" side. Thus, the memory cell allows the same data to be accessed through two ports, but only in the same format or representation. The idea is extended in U.S. Pat. No. 4,610,004, which discloses an integrated circuit having two read ports and two write ports, again allowing data to be accessed in the same format or representation through multiple ports; the device enables data to be accessed at different addresses according to the phase of an "A" side or "B" side clock.
Bit slice data are written to a plurality of memory devices and then accessed in pixel representation in U.S. Pat. No. 4,509,043. One or more bit planes selected to constitute a group define a "surface," and similarly, another group of one or more bit planes defines another surface. The priority of the surfaces is identified so that one surface appears to overlie the other. Multiple ports are not provided in the memory device and therefore, access of the image data selectively in either bit plane or pixel representation through different ports is precluded.
A multi-dimensional parallel storage device is disclosed in U.S. Pat. No.4,570,236. An address computing circuit is provided for each multi-dimensional element produced by scanning an image according to a scanning pattern, enabling the recursive computation of a storage element or a reference array point for a linear storing function to occur after shifting of a window in the displayed image. The data are processed as vectors, allowing multiple storage elements to be simultaneously accessed in vector form, but through only one part.
Advantages of the present invention over the prior art in permitting data stored in an integrated circuit memory circuit to be accessed selectively in bit plane or pixel representation through different ports will be apparent from the attached drawings and the Description of the Preferred Embodiment that follow.